1. Field of the Invention
The present invention relates to analysis of integrated circuits (IC), and more specifically to a method and apparatus for determining the failure rate of an integrated circuit.
2. Related Art
Integrated circuits (IC) are being deployed in large volumes in many different environments. In a typical scenario, a designer generates a design using various software design tools. The design is then used to fabricate potentially a large number of ICs. It is generally desirable that the ICs operate for a long time at least in the conditions intended for.
Accordingly, it may be necessary to analyze the design to determine whether the corresponding ICs are likely to fail over a period of time. Failure rate is a parameter which is used to measure the probability of failure of an integrated circuit over a long period of time. According to one convention, 109 devices are tested for one hour and the number of devices failing is termed as the failure rate. If the failure rate is determined to be unacceptably high, a designer may have an opportunity to redesign the IC to achieve acceptable failure rate.
A well known reason for failure of an integrated circuit is the burning (or disintegration in general) of gate oxide contained in transistors, which form the integrated circuit. As is also well-known, gate-oxide is commonly used as an insulator in the gate terminal of components such as MOSFETs (metal oxide semi-conductor field effect transistor) and the insulator disintegrates typically due to signal overshoots (in positive and negative directions) at the gate terminal.
An overshoot generally refers to the voltage level of a signal which is in excess of the voltage level defining a corresponding logical level. For example, a logical level of 1 may be represented by 1.5 V, and voltage levels exceeding 1.5 V are referred to as overshoots. Similarly, assuming 0 voltage level represents logical value of 0, excessive negative voltage may also be referred to as an undershoot or overshoot (in the negative direction).
The disintegration is particularly problematic in technologies where the gate oxide is very thin (e.g., where manufacturing processes are implemented using sub-micron technology). As the electric field is inversely proportional to the thickness, high voltage levels lead to excessive electric fields, which may cause the disintegration of the gate oxide. Therefore, it may be particularly important to check whether thin gate oxides of the transistors can tolerate any voltage overshoots that occur at the input of different logic gates consistent with the design of the IC.
One challenge in analyzing such integrated circuits (for determining the failure rate) is that typical integrated circuits contain a large number of transistors and analyzing the possible voltage range of the input signals at each transistor may consume long time. The resulting long analysis times may be unacceptable at least in situations where it is desirable to keep the design cycle times short. Accordingly, what is needed is a method and apparatus which determines quickly the occurrence of overshoots at the gates of the transistors in order to ensure a low failure rate of the transistors (and thus of the integrated circuits).
The present invention allows a quick determination of failure rate of integrated circuits (IC) by analyzing the corresponding designs (used interchangeably with IC). The IC is logically partitioned into multiple cells, and default failure in time (FIT) rate is calculated for each cell based on pessimistic assumptions about input signals (xe2x80x9cdefault input signalxe2x80x9d) to the cells. In an embodiment, a default overshoot value is used as a measure of the default input signal.
The design is analyzed further to determine the cells (xe2x80x9covershoot cellsxe2x80x9d) which would actually experience input signals with overshoots exceeding the default input signal (default overshoot overvalue). Exact (i.e., substantially precise) overshoot values are computed only for the overshoot cells by analyzing the cells in more detail. The failure rate of the IC is determined based on the exact overshoot values for the overshoot cells and the default FIT rates for the remaining cells.
As the exact FIT rates are not computed for all the cells, the time to determine the failure rate of ICs is minimized.
According to one more aspect of the present invention, an analyzer tool implementing some of the above described features may maintain a cell library containing multiple types of cells, and the default FIT rates for the type of cells may be pre-computed. When a design is to be analyzed, the pre-computed FIT rates are associated with the corresponding same type of cells. As a result, the computational requirements in determining the failure rate of an IC are further minimized.
In one embodiment, the FIT rates of cells are computed by determining the effective electric field across the gate oxide in each transistor contained in a cell. The FIT rate of a transistor is generally proportional to the electric field. The electric field in turn may depend on the input signal and material using which the transistors are fabricated. The material may be assumed to be the same in the computation of both the actual and default FIT rates. With respect to the input signal for computing exact FIT rates, design tools which analyze the circuit to determine the overshoot signal characteristics may be used.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.